Soitec’s SmartSiC substrates help improve power electronics performance and increase electric vehicle energy efficiency, as well as providing smartphone radio-frequency and power ICs with increased sensitivity and smaller pixel size.
Soitec had been relatively secretive about their SmartSiC wafer specifications until now; only sharing maximum backside contact resistivity values at an ICSCRM presentation in 2022. Recently though, they released data regarding surface finish quality and roughness (SFQR) which could eliminate one back-end fabrication step altogether.
Soitec’s SmartCut Technology
Soitec’s SmartCut technology enables the reuse of high-quality mono-SiC substrates ten times. This results in reduced CO2 emissions during wafer production – an essential benefit for the e-mobility market.
Soitec utilizes its patented process to manufacture engineered substrates used in power electronics for electric vehicles, solar and wind energy generation and industrial equipment components. Their Bernin, France facility is dedicated solely to this production of SmartSiC wafers.
Soitec’s proprietary SmartCut process combines two key techniques – ion implantation and wafer bonding–to produce their UNIBOND SOI wafers. Starting from two bulk silicon wafers bonded together by adhesive to form an oxide layer, hydrogen ions are then implanted through this layer into the silicon to form the SOI structure.
Soitec’s founders embarked on an effort to industrialize SOI technology, then used for specific, low-volume applications. To accomplish this objective, they pioneered Smart Cut: an energy-saving wafer-bonding technique now considered industry standard for SOI manufacturing as well as soon-to-be used to manufacture SiQ wafers – this significantly reduces overall energy usage during wafer fabrication and significantly cuts energy costs associated with wafer fabrication.
SmartSiCTM Engineered Substrates
SmartSiCTM Engineered Substrates enable more powerful and efficient power devices for electric vehicles (EV) and industrial applications by offering higher device performance, better energy efficiency, lower system costs, lighter weight designs and compact structures. The engineered substrate combines a top layer made from single crystal SiC bonded to polycrystalline SiC “handle” wafer for improved device yields and manufacturing yields.
Soitec’s SmartCut technology achieves this result. By taking advantage of the oxidized surface of an initial single-crystal SiC donor wafer to split it at an appropriate depth and bond a thin layer to a lower-resistivity polySiC handle wafer, a highly epi-ready, high performance SiC substrate is created. Furthermore, its reuse reduces energy costs significantly.
Compared to standard silicon carbide (SiC) wafers using conventional nickel-silicide layers, pSiC substrates offer 10x improvements in backside contact resistance, as well as site flatness least squares being improved by more than 2 times. Furthermore, their coarse wafer can be utilized in various wafer-level processes with its low resistivity contributing to superior device performances.
SmartSiCTM Wafers
Silicon carbide (SiC) is an innovative compound semiconductor with significant advantages over traditional silicon power electronics. SiC has several distinct benefits over silicon in terms of power density, component size reduction and weight, lower manufacturing costs as well as energy efficiency enhancement – qualities which make it a key technology in supporting electric vehicle power systems which deliver outstanding performance while having minimal environmental impacts.
Soitec has responded to this strong market demand with polycrystalline SiC (polySiC) substrates made using its SmartCut Technology. This proprietary process uses light ion implantation and wafer bonding to transfer single crystal layers between substrates allowing 10x more monocrystalline SiC to be produced from each batch of polySiC handler wafers.
Germany, as the global leader in electric vehicle production, requires high-quality polySiC wafers. To meet this need, Soitec partnered with Tokai Carbon to develop 150mm and 200mm poly-SiC substrates compliant with Soitec specifications for SmartSiCTM wafers; this partnership should accelerate production ramp-up while creating a critical mass of high-quality, cost-efficient substrates for global EV applications.
SmartSiCTM Substrates
Soitec has pioneered an innovative compound semiconductor technology known as SmartSiC utilizing its revolutionary SmartCut process to split thin layers from high quality SiC donor wafers and bond them onto low resistivity polycrystalline handles wafers for multiple reuses of donor wafers at reduced costs, leading to significant cost and CO2 emission savings. Engineered substrates fabricated using this technology improve device performance, yields and manufacturing yields as well as multiple reuses reducing costs and related emissions significantly.
Soitec’s SmartSiC process combines light ion implantation and wafer bonding, to define and transfer a thin single-crystal layer from one substrate to another without adding new defects or defects to existing ones. Think of it like an atomic scalpel!
Soitec has successfully demonstrated SmartSiC on a 150mm engineered substrate approved for power devices by ST (Euronext Paris). SmartSiC offers the potential to unclog clogged SiC supply chains while simultaneously producing 10x more high-quality engineered substrates per mono-SiC wafer; opening up new pathways toward wider adoption of wide bandgap silicon carbide in applications like eMobility, Industrial and Smart Grid applications. Furthermore, its technology could replace crystal growth furnaces to reduce capex and OPEX costs up to 10x.
SmartSiCTM Process
Silicon Carbide (SiC) power devices have quickly become the go-to solution in electric vehicle (EV) power electronics and other applications, offering improved power conversion efficiency, reduced component size/weight/cost and reduced overall system costs.
Soitec is working hard to meet the rising demand for SiC, by developing engineered substrates based on its Smart Cut technology. The SmartSiC process combines an extremely thin device layer from single crystal donor wafer with polycrystalline carrier wafers; producing substrates using significantly less energy than traditional wafer manufacturing processes.
SmartSiC is an original invention of CEA Leti, where researchers devised an original method of layer transfer. Now a standard in microelectronic industry, Smart Cut allows thickness control at an atomic level for minimum energy usage and maximum performance – an enormous advance for power semiconductors where energy savings are particularly significant. Furthermore, using SmartSiC significantly lowers silicon particle emissions during manufacturing to further decrease environmental impacts along the lifecycle of power electronics components.
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