Silicon carbide epi wafers are essential for power semiconductor devices, which require precise control of thickness and doping. Large surface defects can reduce yields significantly; for this reason, careful inspection and defect mapping must occur prior to production.
Defects divert current, reduce efficiency and can even cause early device failure. Furthermore, defects increase operating temperatures and add costs to end users.
1. Thickness
Sic epi wafers are small discs made of silicon carbide measuring 100 to 150 mm in diameter that are used in power semiconductor devices. To fabricate these power devices, an epi layer with high quality sic must be grown on an electrically conducting substrate; its quality has an immediate bearing on their performance.
SiC epi wafer thickness and dopant levels depend on the operating voltage and device being produced; thicker wafers must be made for devices operating with higher voltages, and uniform thickness/dopant levels throughout.
SiC epi wafers must meet both thickness and dopant levels requirements; additionally they should also be free of surface defects like crystalline stacking faults, micropipes, pits, scratches and stains that may lead to failures of their final device. These defects must also not interfere with performance testing.
Manufacturers must use a rigorous inspection and grading process to ensure their epi wafer is free of defects, such as testing it for contaminant particles by sandblasting it and applying an oxide mask, and inspecting with a scanning electron microscope for defects; once found defect free it is considered high quality product.
2. Carrier concentration
Sic epi wafers are essential materials in power semiconductor applications as they reduce power loss by allowing more current to pass through it and emitting less heat, thus helping reduce energy loss.
Due to their unique properties, epitaxial silicon carbide wafers can be more challenging to produce high quality than their silicon counterparts due to increased temperatures required and poorer growth conditions.
Controlling carrier concentration on a sic epi wafer is key for optimal device performance. Carrier concentration can be affected by several factors, including epilayer growth rate and surface condition as well as defects on its surface.
Optics monitoring techniques are employed to measure the thickness and carrier concentration of sic epi wafers. Fourier-transform infrared (FTIR) reflectometry is an excellent non-destructive means of providing accurate results on layers a few hundred nanometres thick; additionally it can detect stacking faults characterized by triangular-shaped spots or dark spaces with vertical sides in either of its four dimensions [11-20].
Also, it can detect short step bunching, which occurs when steps with different growth rates come into contact and merge together, potentially decreasing current-carrying capacity and leading to reduced efficiency.
3. Large point defects
Large point defects, or lattice defects, are defects which cause current leakage at one or multiple lattice points, typically as the result of foreign matter (downfall) on either a single crystal substrate or epitaxial layer during wafer production. While usually these materials will deposit on the surface, in cases such as SiC they can also occur within its epitaxial layer.
These defects can present serious issues for final semiconductor devices. They may cause voltage drops or even cause device failure; so it is essential that their density remain as low as possible.
Inspection is key to ensure wafers are free from defects, and two main methods exist – surface and subsurface inspections. Surface inspection requires using KOH to etch visible defects to an easily visible size – an ineffective destructive technique not suitable for mass production environments. Subsurface inspection provides more effective, yet more expensive coverage of defects.
Subsurface inspection uses confocal microscopes to detect defects below the epitaxial layer, known as carrot defects, that could interfere with growth or cause dislocations within it. Photoluminescence imaging provides another non-destructive means of subsurface defect detection that can detect micropipes, stacking faults, threading edge dislocations and grain boundaries.
4. Surface roughness
Power semiconductors require excellent surface quality to conduct high-density electric current, which is essential to reaching high yields. As such, epitaxial wafers undergo stringent inspection procedures focused on geometric properties, resistivity, defect assessment and surface roughness assessment.
Researchers studying the quality of 4H-SiC surfaces have discovered that their roughness varies with the C/Si ratio used for growth, with C/Si of 0.85 producing step distribution with heights between 35 nm and 59 nm; researchers believe this macro-step is caused by basal plane dislocation nucleation or slip, while step aggregations could also result from differences between on-axis Si and off-axis Si diffusion length.
4H-SiC wafer roughness depends on its thickness. This was demonstrated through analysis of root mean square (RMS) roughness for on-axis and off-axis 4H-SiC wafers with 20nm radius of curvature; RMS roughness increased with increasing thickness, while off-axis wafers showed lower scaling exponent than their on-axis counterparts.
This trend was further verified through an atomic force microscope (AFM) measurement of roughness between on-axis and off-axis 3C-SiC samples using a standard AFM tip, revealing that on-axis 3C-SiC displays significantly greater roughness compared to off-axis samples.
English 
Swedish