Soitec’s SmartSiC process utilizes a mono-SiC single crystal wafer bonded to an engineered poly-SiC surface, creating a lower resistance substrate which should make implementing SiC devices simpler for customers.
PGC Consultancy’s calculations showed that their substrates could reduce MOSFET total resistance by 20% with their unique resistivity values, according to PGC Consultancy’s estimates.
1. High-Resistivity
Resistance is the currency of power electronics. Every ohm that can be cut off of a MOSFET’s total on-resistance allows it to operate at lower voltage, leading to greater energy efficiency as well as increasing device yield and fab capacity. Any process which increases resistance is of great interest within this industry.
Soitec has developed an engineered substrate called SmartSiC(tm), using its Smart Cut(tm) technology, that offers superior silicon carbide (SiC). It binds an ultra-thin layer of high quality 4H-SiC to an ultra-low resistance polycrystalline SiC ‘handle’ wafer, providing significantly reduced device resistance compared with standard mono-SiC wafers while simultaneously producing smaller die for given resistances; ultimately improving device performance and manufacturing yields.
SiC power industry advancements are of great significance and of immense interest to all who have worked to develop SiC-based power devices. Such devices offer improved power conversion efficiency while allowing lighter, more compact designs for electric vehicles (EVs) and industrial equipment – in turn leading to significant reductions in carbon dioxide emissions compared with traditional silicon systems – something crucial as we advance towards greener future and transition from fossil fuels towards cleaner sources of energy.
2. Low Resistivity
As power MOSFETs become an ever more necessary component in electronic power applications, their low specific on-resistance (SOR) is key in mitigating undesired parasitic effects like switching losses and noise pollution. As demand for SiC power MOSFETs rises exponentially, finding a cost-effective and sustainable method to produce devices with such low SOR is imperative to keeping pace with increasing demands.
The electrical resistivity of porous SiC can vary significantly depending on its composition and processing conditions, especially its porosity (%) and polytype (a or b). Furthermore, presence of second-phase additives can significantly increase or decrease this electrical resistance; they create energy levels close to bandgap which in turn decreases resistance significantly.
Sintering atmosphere has an enormous effect on the electrical resistivity of porous SiC. Sintering in N2 is found to result in lower resistivities than when done in Ar, since N2’s higher solubility of nitrogen increases its phase transformation of b-SiC into a-SiC and enhances N-doping of this material.
Doping porous SiC with various additives is another effective means of altering its electrical resistivity, activating an acceptor-donor compensation mechanism to lower its electrical resistivity and thus decrease electrical resistivity of samples. Unfortunately, an optimal doping concentration has yet to be identified.
3. High Doping
Metal-doped SiC systems exhibit adjustable magnetic and electronic properties based on their hybridization orbitals occupying orbitals near Fermi level, such as adjustable magnetic properties. Based on binding energy and transfer charge characteristics, these materials may be classified either semiconducting or metallic; common examples are Ti-SiC, V-SiC, Cr-SiC, Mn-SiC, Fe-SiC, Co-SiC ZnSiC or GeSiC systems.
Metal-doped SiC wafers often exhibit low and uneven doping concentrations caused by random distribution of impurity atoms during fabrication of SiC epi-layers, creating unbalanced doping distribution and increasing contact resistance of wafers.
Soitec introduced its SmartSiC substrate as a solution, with balanced doping distribution across its entire surface to provide more uniform and predictable material properties than standard wafers do. To address this problem, device performance suffers and yield decreases dramatically as a result. To address this challenge, Soitec developed its SmartSiC substrate. Unlike standard wafers, SmartSiC provides more uniform doping throughout its material surface for increased device performance and yield.
SmartSiC removes the need for pre-conditioning, which lowers manufacturing costs and enhances reliability in power devices. Furthermore, its high doping significantly lowers contact resistance from 50 to 100 uOhm-cm2 down to 5 uOhm-cm2.
SmartSiC substrates exhibit superior defect performance and predicted device yield compared to industry standard reference substrates, matching monolithic and engineered SiC wafers in terms of doping uniformity, thickness tolerances and critical dimension control – with Soitec’s unique ion-implantation technology allowing control over doping concentration in both the p-base and N+ source regions, further increasing performance.
4. Low Contact Resistance
Silicon carbide holds enormous promise as a power semiconductor material, yet its wide use depends on reduced costs and increasing costs-cutting potential in industrial and EV applications. Up until recently, SiC’s high contact resistance limited its use; to improve device performance further it must implement strategies with low contact resistance strategies involving materials and processes that lower this resistance.
Soitec and Resonac have collaborated to produce 200mm (8-inch) silicon carbide substrates known as SmartSiC engineered substrates which offer reduced backside contact resistance (RC) during device fabrication. Their aim is to speed the adoption of silicon carbide for applications like electric mobility, industrial and smart grid applications.
SmartSiC substrates are created using the Smart Cut process, in which a mono-SiC ‘donor’ wafer is permanently adhered to a poly-SiC handle wafer via laser light implantation; once split at an desired depth it is then turned over and adhered permanently to its handle counterpart.
Soitec claim the SmartSiC substrates feature lower backside resistivity for increased front metal deposition density and decreased overall power device contact resistance, as well as lower CAPEX and OPEX costs when replacing mono-SiC substrates with SmartSiC substrates in vertically integrated IDM production facilities, thus saving money both CAPEX and OPEX costs while maintaining production at an equivalent volume.
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